The present invention relates generally to write driver technology for inductive-type magnetic transducers. More particularly, it pertains to a write driver circuit for a three-terminal inductive transducer having improved switching performance.
Inductive-type magnetic transducers are widely used for writing to and/or reading from magnetic data-storage media. Conventionally, transducers write binary-formatted data to a moving magnetic storage medium, such as a rotating magnetic disc, by imparting a bipolar magnetic pattern representing the binary data to the medium. Producing the bipolar magnetic pattern entails alternately forcing electric current through the inductive coil in forward and reverse directions to correspond to the binary data. Current flowing through a conductor generates a magnetic field according to the direction of flow through the coil; thus, reversing the direction of current reverses the magnetic field. Applying the field generated by the coil to the medium coerces a series of adjacent magnetic dipoles of the medium into alignment with the field to form a readable magnetic pattern.
A write driver controls the flow of current through the inductive coil by directing current flow in forward and reverse directions according to an applied input. There are two types of write drivers: one for two-terminal inductive coils and the other for three-terminal inductive coils. Two-terminal coils are formed from a two-ended wound conductor. Write drivers for two-terminal coils are configured by four switches arranged as diagonal pairs, one pair directing current flow in one direction through the coil and the other pair directing current flow in the opposite direction. This arrangement is commonly called an H-bridge or H-switch.
Three-terminal inductive write drivers, on the other hand, require only two switches. A three-terminal inductive coil comprises two oppositely-wound coils connected together at one end to form a center tap. The remaining two free ends are referred to as first and second end taps. The center tap is usually connected to a voltage source and the end taps are connected via first and second switches to a current source. Thus, the first switch controls current flow in the coil section terminated by the center tap and the first end tap, and the second switch controls current flow in the section between the center tap and the second end tap. The oppositely-wound coils generate magnetic fields having opposite polarities. Accordingly, the switches are toggled to produce a bipolar magnetic pattern on a medium adjacent the transducer.
Typically, the switches in write drivers for inductive transducers are built from transistors, such as a bipolar junction transistor. Unlike ideal switches, the bipolar junction transistor switch includes a parasitic base-to-collector (BTC) capacitance that prevents instantaneous changes between conductive (active) and non-conductive states of the transistor. In fact, the BTC capacitance introduces an appreciable delay in the transition between the two states of the transistor switch. The effect of this delay is best explained by reference to the write driver circuit shown in FIG. 1.
FIG. 1 is a circuit diagram of a prior art three-terminal inductive write driver. A resistor R3 and a current source I1 operate a transistor Q4 to enable the write driver. Transistor Q4 is connected between a voltage source Vcc (usually 5 or 12 VDC) and a center tap 12 of inductive coil L via a terminal 10. First and second end taps 14 and 16 of coil L are connected to the respective collectors of NPN switching transistors Q3 and Q5. The emitters of transistors Q3 and Q5 are connected together and to the positive terminal of a current source Iw. The negative terminal of source Iw is connected to voltage source V.sub.EE via a terminal 22. The bases of transistors Q3 and Q5 are connected to the respective emitters of NPN drive transistors Q2 and Q6. The collectors of transistors Q2 and Q6 are connected to source V.sub.cc via terminal 10, and their emitters are connected through respective resistors R2 and R4 to source V.sub.EE. The emitters of PNP input transistors Q1 and Q7 are connected together and through a current source I2 to source V.sub.cc . The collectors of transistors Q 1 and Q7 are connected to respective bases of transistors Q2 and Q6 and to source V.sub.EE via respective resistors R1 and R5.
Functionally, switching transistors Q3 and Q5 form a differential switching pair that applies write current Iw to the end taps 14 or 16 of coil L, according to the higher of the respective transistor base potentials V.sub.BE3 and V.sub.BE5. Transistors Q2 and Q6 are configured as emitter-followers, tracking respective base voltages V.sub.BE2 and V.sub.BE6 and isolating input transistors Q1 and Q7 from switching transistors Q3 and Q5. Like transistors Q3 and Q5, transistors Q1 and Q7 also form a differential pair. However, because transistors Q1 and Q7 are PNP types, they steer current I2 to the transistor Q1 or Q7 that has the lower base potential. In other words, the lower of the two inputs I.sub.N and I.sub.NN controls through which transistor current I2 passes.
Ordinarily, inputs I.sub.N and I.sub.NN are not low at the same time. When input I.sub.N is low, as compared to input I.sub.NN , input transistor Q1 directs substantially all current from source I2 through transistor Q1 and resistor R1 to source V.sub.EE via terminal 22. Thus, the collector voltage V.sub.c1 of transistor Q1 and base voltage V.sub.B2 of transistor Q2 rise from V.sub.EE by an amount equal to (I.sub.C1 -I.sub.B2)R1 to activate transistor Q2. When transistor Q2 is active, i.e. operating in a conductive state, the emitter voltage V.sub.E2 of transistor Q2 and base voltage V.sub.B3 of transistor Q3 are approximately 0.7 volts (one emitter-base junction drop) less than the base voltage V.sub.B2 of transistor Q2. The emitter voltage V.sub.E2 is also appreciably greater than the base voltage V.sub.B5 of transistor Q5, which, because input I.sub.NN is high, is at or near ground potential (V.sub.EE ). Thus, write current Iw flows through the Q3 side of inductive coil L, generating a magnetic field having a first polarity. Reversing polarity of the field requires activating transistor Q5 and deactivating transistor Q3 by switching inputs I.sub.NN and I.sub.N low and high, respectively. Operating input I.sub.NN low activates transistors Q7, Q6, and Q5 to switch write current Iw to the Q5 side of inductive coil L, thereby generating a field having a second polarity, opposite the first. Simultaneously, operating input I.sub.N high deactivates transistors Q1, Q2, and Q3 to terminate current flow to the Q3 side of coil L. Hence, by selectively varying inputs I.sub.N and I.sub.NN, write current Iw may be applied to one or the other side of the coil to write a specific bipolar magnetic pattern on a magnetic medium.
In practice, the prior art driver of FIG. 1 suffers from switching limitations. More particularly, large parasitic base-to-collector (BTC) capacitances exist in switching transistors Q3 and Q5. These BTC capacitances are slow to charge and discharge; hence, they delay the transitions between the conductive and non-conductive operating states of the switching transistors. The parasitic capacitances are a performance liability because the time they require for charging and discharging limits the write frequency of the transducer and the storage density of the medium. The adverse effect on performance is especially acute during a magnetic field reversal.
To reverse the magnetic field, both of the switching transistors are switched, i.e., one is switched from non-conducting to conducting and the other from conducting to non-conducting. In FIG. 1, the BTC capacitances of transistors Q3 and Q5 are charged and discharged by the respective base currents I.sub.B3 and l.sub.B5. The charging base currents are supplied by the emitters of transistors Q2 and Q6. Although transistors Q2 and Q6 are good sources of current, they do not charge the BTC capacitances quickly enough to avoid slewing the output of the transducer.
Discharging the BTC capacitances occurs passively by sinking base currents through respective resistors R2 and R4 to source V.sub.EE. Currents sinking through resistors R2 and R4 produce voltages that support the base potentials of respective transistors Q3 and Q5. Supporting these base potentials keeps the respective transistors activated during discharge, thereby preventing Iw from switching as desired. Moreover, a portion of the discharge flows into the bases of the switching transistors, causing momentary conductive surges in the switching transistors. These momentary surges cause glitching in the output of the transducer. Thus, passive current sinking introduces further slewing and causes glitching in the output of the transducer. Although the size of resistors R2 and R4 could be reduced to speed the rate of discharge, to do so would unacceptably increase the steady-state power needs of the driver without solving the glitching problem. In sum, limitations in sourcing and sinking the base currents of transistors Q3 and Q5 cause appreciable slewing and glitching, generally degrading the quality of data written to a medium, increasing the time required to write data, and restricting the storage density of the medium.